| 摘要 |
PROBLEM TO BE SOLVED: To succeedingly write new information after the recording end part of recorded information so that the disorder of synchronization in the write connection position decreases in reproduction. SOLUTION: A PLL circuit 60 is provided with a control loop 66 which performs the phase lock of a read EFM signal to generate a read clock, and a control loop 68 which performs the phase lock of an ATIP synchronous signal to generate a write clock. The oscillation frequencies of a VCO(voltage- controlled oscillator) 70 are set so as to be equal in both control loops 66 and 68. The PLL circuit 60 is controlled by the control loop 66, and the recorded information is read from the near side of the recording end part of recorded information synchronizing with the read clock when write connection instructed is given from the recording end part of recorded information. In the case of reaching the recording end part of recorded information, the control of the PLL circuit 60 is switched to control by the control loop 68, and then new information is written synchronizing with the write clock. |
