Pulse amplitude modulation (PAM) data communication with forward error correction

摘要

The present invention is directed to data communication system and methods. More specifically, embodiments of the present invention provide an apparatus that receives data from multiple lanes, which are then synchronized for transcoding and encoding. A pseudo random bit sequence checker may be coupled to each of the plurality of lanes, which is configured to a first clock signal A. Additionally, an apparatus may include a plurality of skew compensator modules. Each of the skew compensator modules may be coupled to at least one of the plurality of lanes. The skew-compensator modules are configured to synchronize data from the plurality of lanes. The apparatus additionally includes a plurality of de-skew FIFO modules. Each of the de-skew compensator modules may be coupled to at least one of the plurality of skew compensator modules.

主权项

1. An apparatus for operating 25 Gigabit (25G), 40 Gigabit (40G), 50 Gigabit (50G), or 100 Gigabit (100G) signals in a communication network, the apparatus comprising:
a first plurality of bus lanes configured to receive an encoded and decoded 25G, 40G, 50G, or 100G signals; a pseudo random bit sequence (PRBS) checker coupled to each of the first plurality of bus lanes, and configured to receive a first clock signal A; a plurality of skew compensator modules, each of the skew compensator modules coupled to at least one of the plurality of first plurality of bus lanes; a plurality of de-skew compensator modules, each of the de-skew compensator modules coupled to at least one of the plurality of skew compensator modules; a first bus coupled to an output of each of the de-skew compensator modules, the first bus comprising a first output; a clock rate converter device coupled to the first output of first bus, and configured to receive a second clock signal B; a second bus coupled to an output of the clock rate converter module device; a transcoder module coupled to an output of the second bus, and configured to receive a third clock rate C; a third bus coupled to an output of the transcoder module; a forward error correction (FEC) encoder module coupled to an output of the third bus, and configured to receive the third clock signal C; a second plurality of bus lanes coupled to an output of the FEC encoder module; a plurality of gear box modules coupled to the second plurality of bus lanes, each of the plurality of gear box modules is coupled to a pattern generator module; a first MUX device coupled to a first output of a first gear box module out of a plurality of gear box modules; a second MUX device coupled to a second output of the second gear box module out of the plurality of gear box modules; a first gray mapping Pulse Amplitude Modulation (PAM) encoding module coupled to an output of the first MUX device; and a second gray mapping PAM encoding module coupled to an output of the second MUX device.