Instruction and logic for accelerated compressed data decoding

摘要

A processor includes an execution unit to decode compressed data. The execution unit includes a code information array, a matching logic unit, a code value generator, and a decoder. The code information array includes a pre-computed code length counter and a pre-computed last code. The matching logic unit includes logic using the code information array to match a segment of a payload of the compressed data with a matching code length and a matching code index. The code value generator includes logic to translate the matching code index into a code value. The decoder includes logic to generate decompressed data from the code value and the matching code length.

主权项

1. A processor, comprising:
a front end to decode an instruction, the instruction to decode compressed data; an execution unit; an allocator to assign the instruction to the execution unit to execute the instruction; wherein the execution unit includes:
a code information array, the code information array to include:
a pre-computed code length counter including circuitry to count a number of occurrences for a particular code length, anda pre-computed last code to include a last possible code for the particular code length;a matching logic unit including circuitry to use the code information array to match a segment of a payload of the compressed data with a matching code length and a matching code index;a code value generator including circuitry to translate the matching code index into a code value; anda decoder including circuitry to generate decompressed data from the code value and the matching code length.