| 摘要 |
PROBLEM TO BE SOLVED: To reduce the power consumption of a digital signal processing circuit. SOLUTION: The digital signal processing circuit 1 applies predetermined operation processing to input data din sequentially inputted in a first frequency and generates output data of a second frequency oversampled into n (n is an integer of 2 or more) times. An operation processing part 4 collectively operates continuous m (m is 2≤m≤n) output data in n output data dout of sampling timing after the oversampling. A data storing part 2 stores data of predetermined sampling timing in data generated by the operation processing part 4. An output data storing part 6 stores m data of sampling timing to be outputted. An output data generating part 8 sequentially outputs m output data obtained by the operation processing part 4 in accordance with the second frequency. COPYRIGHT: (C)2008,JPO&INPIT
|
