Automatic pipelining of NoC channels to meet timing and/or performance

摘要

Systems and methods for automatically generating a Network on Chip (NoC) interconnect architecture with pipeline stages are described. The present disclosure includes example implementations directed to automatically determining the number and placement of pipeline stages for each channel in the NoC. Example implementations may also adjust the buffer at one or more routers based on the pipeline stages and configure throughput for virtual channels.

主权项

1. A method, comprising:
generating a Network on Chip (NoC) comprising a plurality of channels and a plurality of routers, the NoC configured with one or more pipeline stages that are positioned at one or more of the plurality of channels in the NoC based on a NoC topology within an associated System on Chip (SoC) floorplan, length of channels from the NoC topology and wire delay normalized to clock frequency; configuring a physical SoC with the generated NoC; wherein a number of the one or more pipeline stages to be positioned is based on a ratio of a length of channels from the NoC topology and a wire delay normalized to a clock frequency.