| 主权项 |
1. A display controller for modulating a reference clock signal to a display panel, wherein the display panel includes a plurality of pixels, the display controller comprising:
a plurality of arbitrating units connected to an external memory by way of a system bus and including first and second arbitrating units, wherein the external memory stores a plurality of graphic data layers including first and second graphic data layers, and wherein the first and second graphic data layers include first and second pixel data corresponding to at least one pixel of the plurality of pixels, respectively, and wherein the first and second arbitrating units fetch the first and second pixel data from the external memory, respectively; a graphics blending unit connected to the first and second arbitrating units for receiving and blending the first and second pixel data, and generating blended pixel data corresponding to the at least one pixel; a pixel data calculating unit connected to the first and second arbitrating units for receiving the first and second pixel data, and determining a size of the first and second pixel data; a latency measuring unit, connected to the pixel data calculating unit and the system bus, for generating a first data rate value based on the size of the first and second pixel data, wherein the first data rate value is indicative of a latency of the system bus; a look-up table (LUT) that stores a mapping between a set of data rate values including the first data rate value and corresponding clock signal modulation values; and a clock divider for receiving a first clock signal modulation value corresponding to the first data rate value from the LUT, and altering a modulation of the reference clock signal based on the first clock signal modulation value to generate a modulated clock signal, wherein the graphics blending unit provides the blended pixel data to the display panel based on the modulated clock signal. |
