| 摘要 |
A memory error detection device for a memory having cells arranged in memory rows and columns, wherein the memory is occupied such that the protection memory row or column has a predetermined reference parity value in a state of integrity, the parity value is chosen so that a row or column error signaling a write-protected state of the memory also results in the reference parity value, with a binary value memory reader of the protection memory row or column. The memory error detection device includes a comparing device designed to calculate a test parity value for the memory values of the protection memory row or column read out and to compare it with a reference parity value expected for the protection memory row or column. The memory error detection device includes a detector designed to take an error measure when the test parity value does not match the reference value.
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