| 摘要 |
1,223,585. Phase comparators; automatic phase control. INTERNATIONAL STANDARD ELECTRIC CORP. 18 Sept., 1969 [23 Sept., 1968], No. 45087/68. Heading H3A. An arrangement for synchronizing digital data comprises a phase comparator in which the incoming data signals are compared with local clock pulses to derive a first signal having a pulse width dependent on the phase difference, and a second signal having a pulse width equal to one clock period and in which these two signals are then combined to provide a signal for adjusting the bias voltage. As described, the data signal is transferred through the shift register SR1 . . . SRN by the clock signal CP. The output from stage SR1 is gated at G1 with the input signal to produce the variable pulse-width signal and the output from SR1 and SR2 are gated at G2 to produce the constant pulse-width signal. These two signals are then combined at X to produce a variable bias which adjust a time constant circuit in the clock generator T1, T2 to vary its frequency. |
