| 摘要 |
<P>PROBLEM TO BE SOLVED: To obtain a block matching arithmetic unit that suppresses power consumption and performs block matching processing to all reference pixels speedily with a small number of circuits. <P>SOLUTION: 2N-1 PE sections are divided into a first SAD operation part 101 comprising n pieces of PE sections, and a second SAD operation part 102 comprising (n-1) pieces of PE sections. A memory interface 103 reads the pixel data of a reference image stored in a memory 104 for outputting to the first SAD operation part 101 and the second SAD part 102, and the second SAD operation part 102 is delayed from the first SAD operation part 101 by one cycle and performs the differential absolute value sum operation between the pixel data of a current image and those of a reference image. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
