| 摘要 |
Interleavers, which spread the bits in a group of length B in the input sequence so that any pair are at least N bits apart in the output sequence, in which delaying circuitry (e.g., one or more shift registers) cooperates with control circuitry to define a plurality of delay paths, each of which is of constant length, the number of such paths being equal to the period, P, of the interleaver (where 2</=P<BN/2). The control circuitry classifies any P successive bits of the input sequence to the P different delay paths, the bits being classified to any such path being spaced P bits apart. The output sequence is derived by sequentially selecting bits from the various delay paths.
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