SYNCHRONIZING A PHASE-LOCKED-LOOP FROM PHASE ENCODED SIGNALS

摘要

In this invention a voltage controlled oscillator provides an output signal which is a clock signal. This is synchronized with the incoming phase-encoded (PE) signal through a phase detector in a phase-locked-loop (PLL). To synchronize the clock signal to the PE signal both signals must be negative-going and positive-going at the same time. This invention corrects the PE signal to a synchronizing signal, by use of an inverting element, whenever the PE signal and clock are not changing in the same direction. A NAND gate connected to the synchronizing signal and the clock senses differences and controls a flip-flop, which inverts the PE signal.