| 摘要 |
PURPOSE:To enable a signal to contain many timing components by performing code conversion which increases change points of a signal by making the ending of each output word different in polarity from the initial bit. CONSTITUTION:A binary data train of repetitive pulse freqency f0Hz is converted into four binary data trains by series-parallel converting circuit PS and 1/4 frequency divider DV. Those four binary data trains are used as addresses of ROM. This ROM has the contents which convert binary four-digit input words into ternary three-digit outputs according to a code conversion table and the data outputs of ROM are made into a ternary pulse train of repetitive frequency 3/4f0 by parallel- series converting circuit SP. |
