Vertical DRAM cross point memory cell and fabrication method

摘要

A method is described for making a vertical DRAM cell which includes a vertical channel field effect transistor having a gate electrode and source/drain elements and a capacitor. A pattern of field oxide isolation in a silicon substrate is provided wherein there are a pattern of openings to the silicon substrate. A pattern is formed of buried bit lines and a pattern of lines of holes with a hole located within each of the openings to said silicon substrate which lines of holes and buried bit lines are perpendicular to one another and which the lines cross at the planned locations of the vertical DRAM cell at the pattern of openings to the silicon substrate. A gate dielectric is formed on the surfaces of the holes. A doped polysilicon layer is formed in and over the holes so that it covers the gate dielectric. The doped polysilicon layer is patterned and etched to form the gate electrode and word lines which are perpendicular to the pattern of buried bit lines. The source/drain elements are formed surrounding the gate electrode in the surface of the substrate by ion implantation using the field oxide and gate electrode and word lines as the mask. The buried bit lines form common and additional source/drain elements. An insulating layer is provided over the pattern of field oxide insulation, word lines and openings to the source/drain elements surrounding the gate electrode. An opening is formed through the insulating layer surrounding the gate electrode. A capacitor is formed in and over the opening through the insulating layer.