发明名称 |
Method for testing an integrated circuit means having a hierarchical organization of at least three levels, and integrated circuit means and integrated circuit suitable for being so tested |
摘要 |
A method for testing a hierarchically organized integrated circuit means first attacks each assembly in sequence thereof, and in each assembly executing an assembly test cycle. Each assembly test cycle within the assembly in question attacks each macro thereof in sequence and conditionally executes therein a test run under selective control of a macro test mode (MTM) signal. The number of hierarchy levels may be other than three. The method may be applicable to separate integrated circuits or to a wired board with a plurality of circuits. |
申请公布号 |
US5477548(A) |
申请公布日期 |
1995.12.19 |
申请号 |
US19930021646 |
申请日期 |
1993.02.16 |
申请人 |
U.S. PHILIPS CORPORATION |
发明人 |
BEENKER, FRANCISCUS P. M.;DEKKER, ROBERTUS W. C.;STANS, RUDI J. J.;VAN DER STAR, MAX |
分类号 |
G01R31/317;G01R31/28;G01R31/3185;G06F11/22;(IPC1-7):G01R31/317;G01R31/318 |
主分类号 |
G01R31/317 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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