| 摘要 |
A PLL circuit is provided which has excellent quick response and noise resistance. A bias data memory circuit 7 previously stores frequency assignment data Da, for assigning the frequency of output signals S1 of VCO 1, as an address and the value, of a control voltage Vc corresponding to the assigned frequency, as bias data Db. A bias voltage production circuit 6 produces a bias voltage Vb of a voltage value provided by the bias data Db output from the bias data memory circuit 7. A switch control circuit 5 compares a phase difference voltage Vd, output from a phase comparison circuit 2, with the bias voltage Vb output from the bias voltage production circuit 6. In this case, if there is a voltage difference between the phase difference voltage Vd and the bias voltage Vb, the switch control circuit 5 turns a switch 4 on to feed the bias voltage Vb to a capacitor 32 of a loop filter, and when the phase difference voltage Vd has become close to the bias voltage Vb, the switch control circuit 5 turns the switch 4 off to stop the feed of the bias voltage Vb. |
