发明名称 METHOD AND EQUIPMENT FOR PHASE DEVIATION CLOCK GENERATION
摘要 PROBLEM TO BE SOLVED: To provide a method and a device for generating plural phase shift clocks on an IC chip. SOLUTION: The device is provided with a PLL 150 provided at a first position and to generate a reference clock 170 and reference voltage 172, local clock generation circuits 152, 154 provided at a second position and a first conductor connected with the PLL 150 and the local clock generation circuits and to transmit the reference clock from the PLL 150 to the local clock generation circuit. Furthermore, the device is provided with a second conductor connected with the PLL 150 and the local clock generation circuits and to transmit the reference voltage from the PLL 150 to the local clock generation circuits. The plural phase shift clocks are generated at a second position by using the local clock generation circuits, according to the reference voltage and the reference clock.
申请公布号 JPH08330948(A) 申请公布日期 1996.12.13
申请号 JP19960152969 申请日期 1996.05.24
申请人 SUN MICROSYST INC 发明人 SASHIYANANDAN RAJIBAN
分类号 H03K5/15;G06F1/06;G06F1/10;H03L7/00;H03L7/06 主分类号 H03K5/15
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