| 摘要 |
PROBLEM TO BE SOLVED: To reduce power consumption at the time of standby by reducing a pattern area of a bit line pre-charge equalizing circuit of a DRAM and reducing a leak current made to flow toward a word line of a short-circuited defective part between a word line and a bit line from a pre-charge power source line. SOLUTION: This memory is provided with plural cell array selecting switches 14 selecting plural memory cell arrays, a bit line sense amplifier 16 provided corresponding to pairs of bit line (BLL, bBLL), (BLR, bBLR) of plural memory cell arrays and connected to the pairs of bit line through the cell array selecting switch, a pre-charge equalizing circuit 15 connected to a pre-charge power source line 40 and the bit line sense amplifier 16 and pre-charging/ equalizing the selected pairs of bit line, and a current limiting element Q20 inserted between the pre-charge equalizing circuit 15 and the pre-charge power source line.
|
