| 摘要 |
The device includes pathways of high-speed lower precision conversion, and paths of slow higher precision statistical correction. The pathway of high-speed conversion effects the desired analogue-to-digital conversion, the pathway of a preliminary correction allows the correction of errors of the high-speed conversion at the instant of start-up, and the pathway of statistical conversion allows the correction of errors of the high-speed conversion in the course of functioning without altering the speed of functioning of the high-speed conversion, but retaining the desired precision. The pathway of high-speed conversion puts in a unique correspondence the amplitudes of samples of input signal (S) to numbers (Nbad), and comprises sampler-holders (EB1, EB2), analogue-to-digital converters (CAN1, CAN2), amplifiers (AMP1, AMP2), a digital-to-anlogue converter (CNA1) for the conversion of signal from amplifier (AMP1), analogue and digital adders (ADA, ADN), a divider (DIV), principal and temporary memory units (MEMO1, MEMO2), and a digital multiplexer (MUL1). The pathway of statistical correction comprises a sampler-holder (EB3) connected to an analogue-to-digital converter (CAN3), slower but of higher precision which can be taken as standard, temporary memory unit (MEMO3), and a digital multiplexer (MUL2) with output connected to the principal memory unit. The statistical correction is carried out by a sequential taking of samples of analogue signal and the measurement in the pathway containing the analogue-to-digital converter (CAN3), and by the preliminary correction, which is activated by the start-up voltage. The pathway of preliminary correction comprises a voltage supply, a monostable circuit, logic and computer units, a digital-to-analogue converter, slow but of higher precision, and an analogue multiplexer with resulting output signal (S). The sequencing is carried out by use of a clock connected to a logic unit for the generation of periodic pulse signals, signal (IMP1) for the control of sampler-holders (EB1, EB2), signal (IMP2) for the control of sampler-holder (EB3), signal (IMP3) for the control of memory unit (MEMO2), signal (IMP5) for the control of multiplexer (MUL1), and signal (IMP6) for the control of multiplexers (MUL1, MUL2). A switch can be used in connection with analogue multiplexer to reduce errors. The sampling can be carried out according to a law of random selection, or according to a deterministic law of pseudo-random selection. The number Nbad = Nb1 + Nb2/A0, or the number (Nbad) is a linear combination of numbers (Nb1, Nb2) with coefficients equal to powers of 2. The pathway of high-speed conversion can contain more than two converters. The conversion system represents the digital value of analogue signal by a number represented by a binary number lower than the sum of binary numbers utilised in converters of the high-speed pathway.
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