| 摘要 |
In a system having a multiplexed address/data bus, initiator and target devices on the bus use special three mode drivers to achieve fast back-to-back read operations without intervening turnaround cycles. These drivers have voltage, current and Hi-Z modes characterized by low output impedance, high output impedence and very high output impedance, respectively. During a first clock cycle, an initiator device places an address on the bus using voltage mode during the first phase of the clock cycle and current mode during second phase. During a second clock cycle, a target device places data on the bus using voltage mode during the first phase of the clock cycle and current mode during second phase. Because a high impedance current mode precedes a low impedance voltage mode, electrical contention problems are eliminated, even if two devices momentarily drive the bus to opposite logical states. Fast back-to-back write operations are also described.
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