发明名称 |
Delay locked loop circuit and its control method |
摘要 |
A delay locked loop (DLL) circuit comprising: a fundamental phase comparator for detecting a fundamental phase difference of two input signals; a delay circuit; a delay control circuit for adjusting a delay time of the delay circuit in response to an output signal of the fundamental phase comparator; and at least one further phase comparator for detecting a phase difference other than the fundamental phase difference such that an amount of change of the delay time is changed in accordance with the fundamental phase difference.
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申请公布号 |
US7035366(B2) |
申请公布日期 |
2006.04.25 |
申请号 |
US20020166123 |
申请日期 |
2002.06.11 |
申请人 |
RENESAS TECHNOLOGY CORP. |
发明人 |
TOKUTOME HIROTO;SAWADA SEIJI |
分类号 |
H03K5/00;H04L7/00;G11C7/22;H03D3/24;H03L7/00;H03L7/06;H03L7/081;H03L7/087;H03L7/091 |
主分类号 |
H03K5/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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