| 摘要 |
In a target processor having a non-protected pipeline, the execution code is typically provided with interruptible code portions and with non-interruptible code portions. The non-interruptible code portions prevent implementation of a real time interrupt that would corrupt the code so that execution could not be resumed. A storage unit is provided that stores a signal permitting a code execution halt even during a non-interruptible code portion. In this manner, a program developer can determine the status of the processor at any point in the code execution. When the execution halt is initiated during a non-interruptible code segment, a bit is set in a bit position of a memory-mapped register. This bit position can be transferred from the target processor to the host processing unit during a transfer of status data.
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