| 摘要 |
A flat panel having at least one non-conductive substrate having a first conductor array on the surface thereof and a dielectric layer on said first conductor array having an exposed flat surface. A first predetermined pattern of vias external through the dielectric layer to pads on each conductor in the array. A second predetermined pattern of vias extend through the dielectric layer to further conductive pads, and an input and through-feed second conductor array is on the substrate with the dielectric layer covering the second predetermined pattern. A conductor material, preferably a gold frit, is in contact with the conductor at the bottom of each via, respectively, and partially filling same to a predetermined level below said exposed flat surface. An integrated circuit chip having an array of a conductive input/output bumps arranged to be congruent with the first and second predetermined patterns is clamped in contact with the conductor material in said vias with a predetermined pressure to make a gas tight contact joints.
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