Transforming a phase-locked-loop generated chip clock signal to a local clock signal

摘要

Electronic circuits and memory circuits are provided for implementing a method for transforming a chip clock signal to a local clock signal. The method includes: generating a first clock signal in response to the chip clock signal, a first control signal and a second control signal; generating a second clock signal by delaying the first clock signal with a second clock delay; generating the first control signal and the second control signal by delaying the second clock signal with a pulse width delay, where the first control signal goes from high-to-low with a control signal delay after the second control signal goes from high-to-low, and vice versa; and generating the local clock signal based on the second clock signal.

主权项

1. An electronic circuit for use in memory array control circuitry to transform a chip clock signal to a local clock signal, the electronic circuit comprising:
base control circuitry including:
a chip clock signal input for receiving the chip clock signal,a first control signal input for receiving a first control signal, anda second control signal output for transmitting a first clock signal,wherein the base control circuitry generates the first clock signal in response to the chip clock signal, the first control signal and the second control signal; delay control circuitry including:
a first clock signal input for receiving the first clock signal, anda second clock signal output for transmitting a second clock signal,wherein the delay control circuitry generates the second clock signal by delaying the first clock signal with a second clock delay; pulse width control circuitry including:
a pulse width control second clock signal input for receiving the second clock signal,a first control signal output for transmitting the first control signal, anda second control signal output for transmitting the second control signal,wherein the pulse width control circuitry generates the first control signal and the second control signal by delaying the second clock signal with a pulse width delay, wherein the first control signal goes from high-to-low with a control signal delayer after the second control signal goes from high-to-low, and vice versa; and driver circuitry including:
a driver second clock signal input for receiving the second clock signal, anda local clock output for outputting the local clock signal,wherein the driver circuitry generates the local clock signal based on the second clock signal.