Sacrificial spin-on glass for air gap formation after bl isolation process in single gate vertical channel 3D NAND flash

摘要

A method for manufacturing a memory device, which can be configured as a 3D NAND flash memory, and includes a plurality of stacks of conductive strips, including even stacks and odd stacks having sidewalls. Some of the conductive strips in the stacks are configured as word lines. Data storage structures are disposed on the sidewalls of the even and odd stacks. Active pillars between corresponding even and odd stacks of conductive strips include even and odd semiconductor films connected at the bottom of the trench between the stacks, and have outside surfaces and inside surfaces. The outside surfaces contact the data storage structures on the sidewalls of the corresponding even and odd stacks forming a 3D array of memory cells; the inside surfaces are separated by an insulating structure that can include a gap. The semiconductor films can be thin-films having a U-shaped current path.

主权项

1. A manufacturing method, comprising:
forming first and second stacks of conductive strips having sidewalls, the stacks including a plurality of layers of conductive material separated by layers of insulating material, and the first and second stack separated by a trench; forming a memory layer over the sidewalls of the first and second stacks and having an outside surface disposed on the first and second stacks and an inside surface opposite the outside surface; forming a layer of semiconductor material over the memory layer, the layer of semiconductor material having an outside surface disposed on the inside surface of the memory layer and an inside surface opposite the outside surface of the layer of semiconductor material; forming a first flowable dielectric material, the first dielectric material contacting the inside surface of the layer of semiconductor material and filling the trench, lined by the memory layer and the layer of semiconductor material, between the first and second stacks; after forming the first and the second stacks of conductive strips, the memory layer, the layer of semiconductor material, and the first dielectric material:
etching a first pattern through the first dielectric material, the layer of semiconductor material, and the memory layer, wherein (i) the first pattern defines a first vertical channel film from a first portion of the layer of semiconductor material adjacent to a first portion of the memory layer contacting the first stack by removing parts of the first portion of the layer of semiconductor material on opposite sides of the first vertical channel film, (ii) the first pattern defines a second vertical channel film from a second portion of the layer of semiconductor material adjacent to a second portion of the memory layer contacting the second stack by removing parts of the second portion of the layer of semiconductor material on opposite sides of the second vertical channel film, and (iii) the first pattern leaves the first dielectric material in between the first vertical channel film and the second vertical channel film; and after etching the first pattern, removing the first dielectric material in between the first vertical channel film and the second vertical channel film.