High speed FPGA boot-up through concurrent multi-frame configuration scheme

摘要

Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).

主权项

1. A programmable integrated circuit device comprising:
a configurable source; a data register that is configured to receive data from the configurable source; a plurality of data line segments comprising configuration random access memory (CRAM), wherein the data register is configured to pipeline the data through each data line segment, and wherein the configurable source is configured to transmit new data to the data register as the data register pipelines the data through each data line segment; and a plurality of address registers, wherein each address register of the plurality of address registers corresponds to a respective data line segment of the plurality of data line segments, and wherein each address register of the plurality of address registers is configured to write the data into respective CRAM of each respective data line segment.