DISPLAY DEVICE

摘要

The plurality of stages of circuit blocks of a driver circuit in a display device include a first transistor and a second transistor. The first transistor is connected at its gate with a first node and controls conductivity between a scanning signal line and a first clock signal line applied with a first clock signal. The first node is at an active potential when at least any one signal of signals output from one stage in each of a forward direction and a reverse direction is at the active potential. The second transistor is connected at its gate with the first node and controls conductivity between the first clock signal line and an input signal line of another stage of circuit block.

主权项

1. A display device comprising:
a plurality of pixels including a pixel transistor respectively, a plurality of scanning signal lines connecting to the pixel transistor of the plurality of pixels, and a driver circuit sequentially applying an active potential to the plurality of scanning signal lines, wherein the driver circuit includes a plurality of stages of circuit blocks as circuits respectively applying the active potential to the plurality of scanning signal lines, a clock signal line applying a clock signal to the plurality of stages, an active signal line applying the active potential, and an inactive signal line applying an inactive potential, the clock signal includes the active potential which can turn on the pixel transistor and the inactive potential which can turn off the pixel transistor, at least one stage of circuit block of the plurality of stages of circuit blocks includes a first transistor, a second transistor, a third transistor, a fourth transistor, fifth transistor, a first node, and a second node, the first transistor connects the clock signal line and the scanning signal line, and applies the clock signal to the scanning signal line when the first transistor is an ON state, the second transistor connects the clock signal line and the first node of a next stage of the plurality of stages, and applies the clock signal to the first node of the next stage when the second transistor is an ON state, the first node is connected to a gate of the first transistor of a present stage and to a gate of the second transistor of the present stage, the third transistor connects the scanning signal line and the inactive signal line when the third transistor is an ON state, the fourth transistor connects the inactive signal line and the first node of the next stage when the fourth transistor is an ON state, the second node is connected to a gate of the third transistor of the present stage and a gate of the fourth transistor of the present stage, the fifth transistor connects the first node and the gate of the first transistor, the fifth transistor has a gate which is connected to the active signal line.