发明名称 |
Method for evaluation of scalable symmetric multiple processor cache coherency protocols and algorithms |
摘要 |
A system and method of evaluating cache coherency protocols and algorithms in scalable symmetric multiple processor computer systems. The system includes scalable 32-byte or larger cache lines wherein one specific byte in the cache line is assigned for write and read transactions for each specific 32-bit processor. The method includes steps to ensure each 32-bit processor writes and reads to and from the specific byte in the cache line assigned to that 32-bit processor.
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申请公布号 |
US2003097527(A1) |
申请公布日期 |
2003.05.22 |
申请号 |
US20010988121 |
申请日期 |
2001.11.19 |
申请人 |
BUSHEY ROBERT D.;LARSON KELLY |
发明人 |
BUSHEY ROBERT D.;LARSON KELLY |
分类号 |
G06F12/00;G06F12/08;G06F13/00;G06F13/16;G06F15/16;(IPC1-7):G06F13/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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