| 摘要 |
<p>1363234 Selective signalling D W HANNA 4 May 1971 [4 May 1970] 12880/71 Heading G4H A receiver for a communication system ineludes a premable detector, a pseudo-random generator with an EXCL-OR circuit for determining bit match, and a threshold detector to determine the existence of a complete bit match. The received signal triggers an oscillator to drive a counter and enable parts of the receiver. The preamble (which is a sequence of ones and zeros alternately) is shifted into a shift register where it is recognized by logic to set a flip-flop which is subsequently reset by the counter. While the flip-flop is set, a shift register, preset with a reference pattern, is shifted with EXCL-OR feedback from stages selected by another reference pattern, to produce the address of the receiver. This address is compared in the first-mentioned EXCL-OR circuit with an address received, the EXCL-OR output being integrated and thresholded to set a flip-flop on equality of the two addresses to gate pulses from the oscillator to a loud-speaker. Alternatively, a machine or transmitter may be controlled.</p> |
