| 摘要 |
PURPOSE:To identify accurately a data at the head of a burst digital signal by using the information of a phase error signal to set the phase of a recovery clock signal forcibly to the state synchronizing with the phase of the burst digital signal. CONSTITUTION:A voltage controlled oscillator 1 outputs an original oscillation clock signal F, which is frequency-divided by 1/N at frequency dividers 2, 5, a phase comparator 3 compares an output C' of the frequency divider 2 with burst digital signal A, a phase error signal D is outputted and passes through a switch circuit 5 and the result is inputted to a filter 4. A burst reception instruction signal B controls the switch circuit 5 so that the phase error signal D passes through only during the period of the required burst digital signal A and the switch 5 is interrupted for the other period. A control voltage E is given to the voltage controlled oscillator 1 from the filter 4 so as to synchronize the output C' of the frequency divider 2 with the burst digital signal A. On the other hand, the phase error signal D is converted into a reset pulse R by a reset circuit 8 to apply the reset control for the frequency division for the frequency divider 5 and to obtain a recovered clock signal G. |
