| 摘要 |
PURPOSE:To speed up a nibble mode or the like by setting the potential of a capacitor constituting a delay circuit to 'H' or 'L' by a control signal. CONSTITUTION:The inverse of a low address strobing signal (RAS), the inverse of a column address strobing signal (CAS) and the inverse of a write enabling signal (WE) are supplied from the external to a DRAM as control signals. Under these control signals, a timing signal phipc is supplied from a timing control circuit TC to a precharging circuit PC for a memory array M-ARY. The circuit TC includes plural delay circuits having a function for selectively shortening a delay time by forcedly turning the capacitor potential to the 'H' or 'L' level. Consequently, the repeating operation of the nibble mode or the like in the DRAM can be speeded up. |
