发明名称 Delay locked loop circuit and signal delay locking method
摘要 A delay locked loop circuit and signal delay locking method are provided. First, the start-up circuit minimizes the delay time between an output signal and a reference signal during an initial period. Secondly, the phase correction circuit increases the delay time during an correction period. The present invention ensures that the phase difference between the output signal and the reference signal is correctly detected by the delay locked loop circuit, so that harmonic lock and phase ambiguity can be avoided.
申请公布号 US7262647(B2) 申请公布日期 2007.08.28
申请号 US20060307803 申请日期 2006.02.23
申请人 NOVATEK MICROELECTRONICS CORP. 发明人 CHOU KUO-YU
分类号 H03L7/06 主分类号 H03L7/06
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