Second-cache driving/controlling circuit, second cache, RAM, and second-cache driving/controlling method

摘要

A circuit for driving and controlling a second cache that is incorporated in a processor and comprises a plurality of RAM. The circuit comprises a second-cache control unit 1 A and a chip-enable control unit 61 . The second-cache control unit 1 A receives an access request for an access to the second cache and designates some of the RAMs, which need not operate, in accordance with the type or address of the access request, or both. The chip-enable control unit 61 outputs an intra-macro stop-instructing signal to the RAMs that have been designated by the second-cache control unit 1 A.