FREQUENCY SYNTHESIZER WITH A PHASE-LOCKED LOOP WITH MULTIPLE FRACTIONAL DIVISION

摘要

A frequency synthesizer comprises a single phase-locked loop controlled by a reference clock formed by a voltage-controlled oscillator, a programmable divider with variable division rank M, a phase detector, and a loop filter. It also comprises a predetermined number n of fractional division structures, each implementing a frequency step P i x F ref lower than the reference frequency F ref. Each fractional structure is coupled in parallel with said programmable divider to add to said division rank M fractional increments P i such that the ratio between the frequency F vco provided by said oscillator and said reference frequency be defined as a function of said increments P i by the relationship : (see fig. I) Application : any type of product or system requiring a frequency synthesizer, in particular communications system with frequency agility.