| 摘要 |
<p>1,193,804. Pulse discriminating circuits. INTERNATIONAL BUSINESS MACHINES CORP. 5 Feb., 1969, No. 6115/69. Heading H3T. [Also in Division G4] A pulse selecting circuit comprises an input gate receiving the input pulse train, a sawtooth generator having a fixed amplitude flyback and which opens the gate when the ramp exceeds a given level, the generator being triggered by the output from the gate, a further gate receiving the output of the first and being enabled by the ramp generator when the flyback does not pass a given threshold level due to the spacing between the triggering pulses and thus the amplitude of the ramp exceeding a given value. The invention is applied to a train of pulses from a magnetic storage disc, data being represented by pulses D1, Fig. 4a preceded by a clock pulse C and the address by pulses 54, 55 not preceded by a clock pulse. The input circuit comprises a combination of gate 14 and a flyback and ramp generator having a fixed amplitude flyback, described in Specification 1,126,160 and with reference to Fig. 2 (not shown). Briefly, the ramp generator produces an output 4b which, following a clock pulse, provides a gating pulse 4c lasting until the ramp reaches a valve L, the pulse closing gate 14 long enough to block the next data pulse so that only clock pulses and address pulses (i.e. pulses not preceded by a clock pulse) are selected by gate 14, the output of the gate being used to trigger the flyback. The circuit also selects at 15 (Fig. 2) the data pulses. The gating pulses 4c and the selected clock and address pulses from 14 are applied to an AND gate 59 to produce pulses 4d coincident with clock and address pulses. Gates 60 and 63 are crosscoupled to form a bi-stable circuit. It is set by pulses from 14 and reset when the flyback passes threshold L, to produce pulses 4(e). Thus it remains reset during the absence of clock pulses. Gates 68 and 70 also form a bistable circuit. It is controlled by 4e and by the output of an AND gate 66 itself controlled by 4e and the output of gate 14 so as to produce narrow pulses concident with clock pulses and pulses starting at the second address pulse and ending at the next clock pulse 4h. These pulses control a gate 72 which also receives the output of a gate 14 so as to produce pulses coincident with the second address pulse and the next clock pulse (4k). In order to prevent zero drift and pulse timing errors, shown dotted in 4(b), from causing false switching of bi-stable circuit 60, 63, a monostable circuit 74 produces inhibit pulses during this period. The second bi-stable circuit may be replaced by a timing circuit.</p> |
