| 摘要 |
PURPOSE: To improve the accuracy of synchronism even when clock frequency is low by setting up a selection circuit to a frequency division ratio when a phase difference between an input clock signal and an output of a frequency divider is less than a target value, and when the difference exceeds the target value, setting up the frequency dividing ratio to '1' or a smaller value. CONSTITUTION: A phase comparator 1 compares the phase of an input clock signal A with that of an output B from a frequency divider 5 and sends its output to a voltage controlled oscillator(VCO) 4 through a low pass filter 2 and an amplifier 3. The VCO 4 sends the sent output to a 1/2 frequency dividing circuit 7 and a selection circuit 8. The circuit 8 receives plural outputs, selects the frequency dividion ratio of the circuit 7 and supplies the selected value to the frequency divider 5. The signals A, B, an L level part signal C indicating a steady phase error range and an L level signal D indicating target phase synchronizing range are inputted to a control circuit 6, and when a phase difference A-B is less than target value, the circuit 8 is set up to the frequency division ratio 2. When the phase difference A-B exceeds the target value, the frequency dividing ratio is set up to '1' or a smaller value. |
