| 摘要 |
PURPOSE:To enable a titled circuit to extract timing signals stably and surely even under conditions that frequency causes mixing of noises and omission of timing signals by controlling passing of input timing signals through a gate circuit. CONSTITUTION:Timing signals inputted from an input terminal 1 include not only true timing signals but also mixed noises, omission of timing signals. These signals are inputted into a gate circuit 21, passes through the gate circuit 21 only in the period of permission of passing, and reset a frequency dividing circuit 50. Thus, only true timing signals pass the gate circuit 21, and noises mixed in timing signals are removed perfectly. Accordingly, the frequence dividing circuit 50 outputs signals synchronized with true timing signals, and even in omitted part of timing signals, timing signals that keep the state prior to omission at expected timing are outputted.
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