发明名称 DYNAMIC RANDOM ACCESS MEMORY
摘要 A DRAM according to the invention has noise-eliminating circuits. Each of the circuits has an output side thereof connected to a corresponding word line. At the time of a voltage stress examination, each of the circuits is controlled to be in an on-state thereby transmitting a voltage stress, input an input side thereof, to the word line. At the time of normal operation, the input side of the circuit is connected to an earth node, and each of the circuits is turned on and off in accordance with a signal output from a corresponding one of word line-selecting circuits or with the level of a corresponding one of the word lines.
申请公布号 KR960000889(B1) 申请公布日期 1996.01.13
申请号 KR19910024732 申请日期 1991.12.27
申请人 TOSHIBA K.K. 发明人 TANAKA, HIROAKI;KOYANAGI, MASARU
分类号 G01R31/28;G11C11/401;G11C11/407;G11C11/408;G11C29/06;G11C29/50;H01L21/66;(IPC1-7):G11C11/40 主分类号 G01R31/28
代理机构 代理人
主权项
地址