| 摘要 |
PURPOSE:To improve the effective gate density of an LSI of a master slice, by constituting input/output cells by BCs (basic cells) for constituting a logic circuit. CONSTITUTION:A first input/output cell region 20 by BCB cells is provided at the peripheral position of a chip in a BC region 2. A second input/output region 21 by BCB cells, which are added in the chip, are provided. The BCB cells are basic cells (BC buffer cells) for constituting a logic circuit. The first input/output cells 20 are formed by using the BCB cells at the positions, where conventional dedicated input/output cells are arranged at the periphery of the chip. With respect to the shortage in the input/output cells, the second input/ output cells 21 are formed by using the BCB cells at arbitrary places in the chip. Thus the shortage is corrected. At this time, the number of input/output terminals is increased by the addition of the second input/output cells 21. Since the gate region 2 is reduced, the balance point between the number of the input/ output terminals and the number of the gates is always present. Thus the LSI, in which a hollow region is not present in a chip, can be designed.
|
