| 摘要 |
In a semiconductor integrated circuit device produced in a master slice system, power source wirings are placed over the peripheral portion of a basic cell array and auxilliary power source wirings are extended over the basic cell array. A first power source wiring is supplied with a first power source voltage and a second power source wiring supplied with a second power source voltage, both thereof being located adjacent to the basic cell array, and are both formed on separate layers one above the other so as to overlap and parallel each other. The auxiliary power source wirings are formed one above the other, in the same wiring layers as the first power source wiring and the second power source wiring. A third power source wiring and a fourth power source wiring are disposed in the same wiring layers as the first power source wiring and the second power source wiring, so as to be juxtaposed with the first power source wiring and the second power source wiring, respectively. The third power source wirings and the fourth power source wirings are arranged to overlap and parallel each other. The first power source wiring and the fourth power source wiring are supplied with the same first power source voltage while the second power source wiring and the third power source wiring are supplied with the same second power source voltage. |
