| 摘要 |
A Run/Stop (R/S) pin 12 on a microprocessor chip is asserted to access and hold an idle mode. An additional pin, "acknowledge pin" 16, is provided to indicate when the microprocessor is in the idle state. The idle mode is asserted at an instruction boundary that is, when the execution unit 22 has completed all its modifications of registers, flags, and memory for a first instruction, but before it begins execution of the next instruction following in the pipeline. In the idle mode, the decoder 18 does not issue instructions into the pipeline, but the clock operates normally and other microprocessor functions are operable. A port 40 may be provided, with a secondary control unit 42 for issuing simple instructions directly to the execution unit, bypassing the normal instruction issue process. The present invention can be useful for implementing debugging and remote diagnostic systems, and also for synchronizing microprocessors running in parallel. <IMAGE> |
