| 摘要 |
<p>A variable length code decoding circuit includes a decoding table storing data, which has an upper field selectively indicative of a meaning of the code and an address for next access, selected depending upon a state transition upon decoding the variable bit length code per n bits (n is an integer greater than or equal to 2), an intermediate field indicative of a shifting magnitude of the shift register (116) upon completion of decoding, and a lower field indicative of a state of code decoding. The bit sequence of the variable bit length code in a shift register (116) is shifted in a magnitude corresponding to a shifting ,magnitude indicated in the intermediate field when data indicative of the code decoding state in the lower field of the data read out from the decoding table storage means (112) indicates completion of decoding and corresponding to n bits when the data indicative of the code decoding state in the lower field indicates continuation of decoding. An address for accessing the decoding table (112) is generated by replacing the intermediate field and the lower field with leading n bits of the shift register (116). <IMAGE></p> |
