| 摘要 |
PURPOSE:To reduce the circuit scale by reducing two frame pulse generating counters which have been required for a conventional circuit into one through the common use of the counter for required functions. CONSTITUTION:A selection circuit 2 selects either an external input clock signal S2 or an internal clock signal S1, and a frame pulse generating counter 4 counts up any selected clock signal, outputs a counter load pulse signal S16 at full- count, loads a 1st counter initial value (S5-S9) and generates an output frame pulse signal S15. When the selection circuit 2 selects the external input clock signal S2, a load pulse generating circuit 3 receives the external input frame pulse signal S3, generates the counter load pulse signal S4, and a counter initial setting section 5 generates a counter initial value operation signal S6 used to set a 2nd counter initial value (S5-S9) to a frame pulse generating counter in response to a counter load pulse signal S4. |
