| 摘要 |
A latch output driver including an output driver circuit having a pull-up transistor and a pull-down transistor connected in series, wherein the pull-up transistor has a drain connected to an upper power supply voltage and a source connected to a drain of the pull-down transistor and the pull-down transistor has a source connected to a lower power supply voltage. The latch controlled output driver also includes a first latch circuit having an output connected to the gate of the pull-up transistor and a second latch circuit having an output connected to the gate of the pull-down transistor. A control circuit is connected to the first and second latches, wherein the control circuit may selectively disable and enable the latch controlled output driver in response to a control signal. A driver output is connected between the pull-up and pull-down transistors, wherein the output driver is in an open state when the latch controlled output driver is disabled by the control circuit. A data circuit is connected to the first and second latch circuits, wherein the data circuit stores the state of the first and second latches present when the latch controlled output driver is enabled and restores the state of the first and second latches when the latch controlled output driver is enabled after being disabled.
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