| 摘要 |
PURPOSE: A voltage level detector is provided to reduce current consumption by preventing a current path from a power supply voltage to a ground voltage during activation of an input pulse. CONSTITUTION: A PMOS transistor(P1) supplies a power supply voltage(Vdd) to a Nd1 node in response to an inversed version of a control signal(peqode), and a PMOS transistor(P2) transfers a potential of the Nd1 node to a Nd2 node when a potential of the Nd2 node is lower than that of the Nd1 node. An NMOS transistor(N5) is switched by a potential of a Nd4, and an NMOS transistor(N4) connects Nd9 and Nd3 nodes in response to the inverted version of the control signal(peqode). PMOS transistors(P3-P5) are connected to transfer the power supply voltage to an Nd4 node according to the potential of the Nd2. A NAND gate(NAND1) is supplied with a signal on the Nd4 node and the control signal(peqode), NMOS transistors(N1-N3) are connected to transfer a ground voltage to the Nd4 node according to the potential of the Nd2 node. A NAND gate(NAND2) is supplied with the control signal(peqode) and a signal on the Nd6 node, which is supplied with an output of the NAND gate(NAND1). A flip-flop(10) receives a signal on the Nd6 node as a set signal and a signal on the Nd7 node as a reset signal, and latches a signal on the Nd6 node to output the latched signal to a Nd8 node.
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