| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a clock generation circuit capable of generating clock of Duty 50%. <P>SOLUTION: A clock generating circuit 31 for dividing the frequency of a multiplication clock based on frequency dividing ratio data, comprises a frequency dividing ratio identifier 1 for identifying whether frequency dividing ratio data are even-numbered, odd-numbered or decimal, delay tap equipment 2 and a cycle counting latch frequency divider 3. If the frequency dividing ratio identifier 1 identifies frequency dividing ratio data as decimal, the multiplication clock is delayed by the delay tap equipment 2 to generate a delay clock, and the cycle counting latch frequency divider 3 divides the frequency of the multiplication clock using an edge of the delay clock and an edge of the multiplication clock. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
