| 摘要 |
PURPOSE:To recover a high speed clock by providing a control section comprising an accumulator, a 2nd D/A converter and a comparator to a clock recovery circuit comprising a phase locked loop. CONSTITUTION:When demodulated digital data c2 are inputted to a phase detector 1, the detector 1 detects a lead/lag of recovered clocks a2, b2 with respect to a zero cross point of the data c2. The delay/lag is outputted to a loop filter 2 as phase difference data d2. The loop filter 2 smoothes the data d2. A control section 6 controls the filter 2 and data input to the accumulator 4 based on output data of the filter 2. Then output data e2, f2 of the filter 2 and the adder 4 are inputted respectively to D/A converters 3, 5, from which analog voltage signals g2, h2 are obtained and they are added at an adder section 7. An output voltage i2 of the adder 7 controls a VCO 8. An output of a VCO 8 is subject to 1/2 frequency division as clocks a2, b2. |
