| 摘要 |
PURPOSE:To obtain a stable pattern by keeping a neutral point potential of vertical output transistors (TRs) in push-all connection to a constant value in a vertical deflection circuit to stabilize a DC bias in both synchronous and asynchronous state. CONSTITUTION:A vertical synchronizing signal obtained from a synchronizing separator circuit 1 is fed to an input terminal 5 via a frequency division and discrimination circuit 3 and a vertical drive circuit 4 at synchronizing state. A TR6 is turned on in this case, a sawtooth wave of vertical period is generated to a TR8 constituting a differential amplifier 7, after the wave is amplified by an amplifier stage 10 and an output stage 13, the result is fed to a deflection coil 17 as a sawtooth wave deflection current. In taking the charged and discharged electric charges of a charge/discharge capacitor 20 equal to each other into consideration, the neutral point potential VCNT of the output stage 13 is expressed by a specific equation and a neutral point potential V'CNT is expressed by a similar equation even at the asynchronous state. In deciding the condition of VCNT=V'CNT in equation, the neutral point potential is kept to a constant value at all times independently of the synchronous or asynchronous state. |
