发明名称 ERROR DETECTING CIRCUIT
摘要 PURPOSE:To discriminate a faulty area of the address information by storing a check bit, the write data and the address information into a memory array and detecting an error based on those information read out of the memory array in a reading action state. CONSTITUTION:The address data AD is inputted to an address circuit 4 with a write request. While the circuit 4 outputs the address information AI to circuits 60, 82, 83 and a memory array 2 respectively and outputs an AI parity AP to the circuit 83. The check bit CB given from the circuit 60, the write data WD and the information AI are stored in a real address of the array 2 designated by the circuit 4. When a read request is received, the circuit 4 receives the data AD and designates the real address of the array 2. Then the RD, CB and AI' are read out of the array 2 and the Sy (syndrome) is inputted to an error detecting circuit 81 from an Sy generating circuit 80 for output of an ADE. The comparator 82 outputs an ACE when no coincidence is obtained between the AI and the AI'. The circuit 83 receives the AP and the AI and outputs an APE.
申请公布号 JPH01292550(A) 申请公布日期 1989.11.24
申请号 JP19880122106 申请日期 1988.05.20
申请人 NEC CORP;KOUFU NIPPON DENKI KK 发明人 TACHIBANA YOSHIMI;ISHIKAWA HISASHI
分类号 G06F12/16;G06F11/22 主分类号 G06F12/16
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