| 摘要 |
PURPOSE: To stably operate a synchronizing process by providing a line interface circuit, digital phase-locked loop device(DPLL), reset means and initialization setting means. CONSTITUTION: When the RESET input command of line interface circuit 201 is activated, the circuit 201 is isolated from a G.703 network 100. The RESET input lead of the circuit 201 is disactivated, the circuit 201 is connected to the network 100. At this time, transmission to an Xmit pair 105 is enabled, while matching steps with an Xmit clock appearing at a lead 204. Conversely, an analog signal received from an Rce pair 106 is demodulated, and data and a reception clock are extracted from a modulate signal. This is achieved by activating the RESET input lead of DPLL. |
