发明名称 FRAME SYNCHRONIZING CIRCUIT
摘要 PURPOSE:To shorten a synchronism acquisition time at the time of erroneous detection of frame synchronism. CONSTITUTION:A comparing part 5 outputs a detection signal when the output of an operation part 3 exceeds a threshold. A back protection part 6 starts back protection by the first detection signal to out-put, a count start signal. A count part 7 starts counting of the bit position by the count start signal. A storage part 8 integrates the frequency in output of the detection signal in each bit position. When discriminating that synchronism is not settled yet, the back protection part 6 outputs a synchronism unsettled signal. A control part 9 calculates the bit position, where the frequency in output of the detection signal is maximum, from the storage part 8 by the synchronism unsettled signal and compares it with the bit position from the count part 7 and outputs the difference as the shift time. The back protection part 6 starts the back protection operation again after the shift time, and this operation is repeated if frame synchronism is not settled yet.
申请公布号 JPH06209312(A) 申请公布日期 1994.07.26
申请号 JP19930017868 申请日期 1993.01.11
申请人 NEC CORP 发明人 HASHIMOTO SHINJI
分类号 H04J3/06;H04L7/08;H04L7/10 主分类号 H04J3/06
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